Offline & tactical
AI agents
Deploy local multimodal intelligence on autonomous swarm nodes and field systems that cannot depend on cellular, cloud, or continuous network access.
LOCAL AGENT · DISCONNECTED OPERATION
Model-to-hardware compiler · FPGA / ASIC path
Compile AI
into hardware.
Turn AI models into deployable hardware for fast, private, offline inference.
CORE VALUE · AUTOMATED MODEL-SPECIFIC RTL AND FPGA IP GENERATION
ENGINEERING MODEL / V1
PSDUAL-CORE
ARM A9PETALINUX
ARM A9PETALINUX
PLARTIX-7
LOGIC8 RECONFIGURABLE SLOTS
LOGIC8 RECONFIGURABLE SLOTS
OV CAMERA INPUTDIRECT FPGA STREAMmicroSD / BOOT
512 MB DDR2 · FLAT-SAT READY
KICAD 3D VIEW · FLAT-SAT EVALUATION VEHICLE
01Evaluation formatPQ60 PocketQubeEngineering Model / Flat-Sat kit
02System on chipZynq-7020Dual-core ARM A9 + Artix-7 PL
03Programmable logic8 independent slotsDynamic partial reconfiguration
04Radio + powerSub-GHz / 2.4 GHz · < 5 WLoRa · (G)FSK · Sigfox · LR-FHSS
01 / Technical image gallery
See the hardware
from every layer.
CLICK ANY IMAGE TO
OPEN A LARGER VIEW
Engineering layout view showing the compact board envelope, placement, and routed signal paths.
Top-side rendering of the evaluation board and its high-density component regions.
Bottom-side view highlighting the connector field, routing, and supporting circuitry.
Vivado block design showing how the processing system, interfaces, memory, and programmable logic connect.
Floorplan capture showing the slot regions and dense interconnect used for dynamic payload reconfiguration.
02 / AI output layer
GPT-class AI
without the cloud.
Local inference turns raw inputs into decisions before anything leaves the device. The model can interpret images, telemetry, commands, and sensor streams, then produce a useful answer, action, or compact semantic message.
- Understand: identify objects, events, anomalies, and mission context locally.
- Respond: run multimodal prompts and commands without round-tripping to a data center.
- Communicate: send semantic tokens when the device needs to share its conclusion.
LOCAL FIRSTGPT-CLASS INFERENCE FOR DISCONNECTED SYSTEMS
CAMERA · TELEMETRY · COMMAND · SENSOR INPUT
REAL-WORLD
INPUT→GPT-CLASS
EDGE
INFERENCE→ANSWER
ACTION
INSIGHT
INPUT→GPT-CLASS
EDGE
INFERENCE→ANSWER
ACTION
INSIGHT
Run the intelligence next to the data. The device produces a useful answer or action locally, with optional compact output when a link is available — a projected architecture target, not a measured result.
PRIVATE BY DEFAULT · OFFLINE CAPABLE · ENCRYPTED OUTPUT
03 / Model fit study
More parameters.
Still at the edge.
2-BIT TERNARY STORAGE
PLANNING COMPARISON
1.7BPARAMETER CLASSSmolLM-1.7B planning case
427.5MB2-BIT WEIGHTSProjected ternary footprint
512MBDDR2 TARGETExternal memory envelope
< 5WPOWER TARGETEngineering model planning target
A compact model footprint makes local inference practical on constrained hardware. The figures below are planning estimates, subject to runtime buffers, firmware overhead, and final hardware validation.
| Model | Parameters | Target intelligence (MMLU) | FP32 size | INT8 size | 2-bit ternary weights | 512MB DDR2 fit |
|---|---|---|---|---|---|---|
| SmolLM-135M | 135M | ~39.2% | 540MB | 135MB | 33.75MB | YES · ~7% |
| SmolLM-360M | 360M | ~56.0% | 1.44GB | 360MB | 90.00MB | YES · ~18% |
| SmolLM-1.7B / SmolLM2 | 1.71B | ~68.0% | 6.84GB | 1.71GB | 427.50MB | YES · ~83% |
| GPT-2 Small | 124M | ~35.0% | 496MB | 124MB | 31.00MB | YES · ~6% |
| GPT-2 Medium | 355M | ~42.0% | 1.42GB | 355MB | 88.75MB | YES · ~17% |
| GPT-2 Large | 774M | ~45.0% | 3.10GB | 774MB | 193.50MB | YES · ~38% |
| GPT-2 XL | 1.55B | ~48.0% | 6.20GB | 1.55GB | 387.50MB | YES · ~76% |
IMPORTANT FIT IN DDR ≠ FIT ENTIRELY IN FPGA ON-CHIP MEMORY · WEIGHTS STREAM FROM EXTERNAL MEMORY INTO SMALL ACCELERATOR BUFFERS · MMLU VALUES ARE INDICATIVE TARGETS · RUNTIME MEMORY, ACCURACY, PERFORMANCE, AND POWER STILL REQUIRE VALIDATION · VALUES ARE PLANNING ESTIMATES
04 / Deployment targets
Run AI
where cloud fails.
LOCAL INFERENCE
NO CONSTANT CONNECTION
Offline & tactical
Orbital & high-altitude
AI inference
Process EO, sensor, and radar streams on-device, extracting actionable intelligence in orbit before selectively sharing results over a constrained link.
IN-ORBIT AI · DOWNLINK RELIEF
Remote autonomous
AI devices
Unattended buoys, wilderness sensors, and industrial nodes can reason over local data, detect anomalies, and act without uploading everything.
MARITIME · WILDERNESS · INDUSTRIAL
05 / AI software toolchain + developer integration
Config in.
Hardware out.
This is more than a compiler or software emulator. The planned generator can take a compatible pre-existing PyTorch model from sources such as Hugging Face, convert its weights into a supported ternary format, and create the custom hardware IP and RTL needed to run that model on an edge platform.
The output is hardware implementation, not just a smaller parameter file: model operators become deployable RTL modules, platform scripts, and host tables. Existing .v or TCL inputs can be incorporated for the target FPGA toolchain, while the generated RTL can also provide an ASIC-oriented handoff path.
- MODEL IMPORT: bring a compatible PyTorch checkpoint or Hugging Face model into the conversion workflow.
- TERNARY CONVERSION: transform supported weights into a compact 2-bit representation for smaller edge-device storage.
- CUSTOM HARDWARE GENERATION: generate model-specific RTL and hardware IP so the supplied model executes in hardware instead of relying on software emulation.
- FPGA-AGNOSTIC OUTPUT: export portable Verilog, TCL, and integration metadata that can be adapted to different FPGA platforms and toolchains.
- FPGA OR ASIC PATH: use the generated RTL for an FPGA deployment today or as a reusable handoff for a future custom ASIC flow.
- HONEST PLANNING: the generator reports compatibility, fit, resource expectations, or a clear rejection reason before build.
01
IMPORT MODEL OR HDL
Bring a compatible PyTorch or Hugging Face checkpoint, or provide existing Verilog and TCL for the target platform flow.
02
CONVERT TO TERNARY
Transform supported weights into a compact 2-bit representation and prepare the hardware-oriented data layout.
03
GENERATE CUSTOM RTL / IP
Map the model operators into model-specific RTL and hardware IP so inference runs in hardware rather than through software emulation.
04
EXPORT PLATFORM OUTPUT
Produce portable Verilog, TCL, host tables, and integration metadata for the chosen FPGA toolchain or an ASIC-oriented RTL flow.
05
HARDWARE APP LIBRARY
Discover and reuse hardware applications such as DSP pipelines, vision blocks, sensor interfaces, and mission-specific accelerators.
06
PROFILE / DEPLOY
Test fit, accuracy, memory use, latency, and power on the selected hardware target before moving toward integration.
PETALINUX / NATIVE C++ APIFLIGHT SOFTWARE
// Load a mission core at runtime
auto slot = load_fpga_slot("transformer");
configure_model(slot, "/models/edge.bin");
stream_camera(slot, camera_input);
read_semantic_output(slot, &result); 06 / AI hardware architecture
Shape the
inference engine.
The generator emits portable hardware outputs and integration metadata for the selected FPGA platform, while preserving a path toward custom silicon. Dynamic partial reconfiguration can support hot-swappable AI and signal-processing modules without rebuilding the whole design.
AVAILABLE AI LOGIC SLOTS8HOT-SWAPPABLE INFERENCE REGIONS
VIVADO FLOORPLAN / ZYNQ-70208 PR REGIONS
07 / Reference architectures
From model graph
to FPGA fabric.
MULTIMODAL MODEL
HARDWARE IMPLEMENTATION
TERNARY TRANSFORMER · HARDWARE DATAFLOW
Hardware-oriented reference showing ternary embeddings, attention, FFN processing, KV cache, residual paths, and the ternary linear engine.
INTERNAL LOGIC ARCHITECTURE · FPGA IMPLEMENTATION
Implementation view showing DDR streaming, DMA paths, crossbar routing, control hubs, and eight reconfigurable slots.
08 / B2B offline AI evaluation programme
Put GPT-class
intelligence in the loop.
Request an evaluation kit, download the software or hardware datasheet, or read the whitepaper. Tell us where you need AI to run without the cloud.
MODEL LOAD
↓
LOCAL INFERENCE
↓
EDGE ACTION
↓
LOCAL INFERENCE
↓
EDGE ACTION